EDA 设计7人表决器VHDL程序设计
2009-06-07 18:55阅读：
程序1，，，，，，，，，，，，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bjq7 is
port (a,b,c,d,e,f,g:in std_logic;
y:out
std_logic);
end;
architecture one of bjq7 is
begin
process(a,b,c,d,e,f,g)
variable cnt:integer range 0 to 7;
begin
cnt:=0;
if a='1' then cnt:=cnt+1;end if;
if b='1' then cnt:=cnt+1;end if;
if c='1' then cnt:=cnt+1;end if;
if d='1' then cnt:=cnt+1;end if;
if e='1' then cnt:=cnt+1;end if;
if f='1' then cnt:=cnt+1;end if;
if g='1' then cnt:=cnt+1;end if;
if cnt>3 then y<='1';
else y<='0';
end if;
end process;
end;
程序2，，，，，，，，，，，，，，，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bjq7 i
s
port (input:in std_logic_vector(6 downto 0);
cnt:out std_logic_vector(2
downto 0);
led:out
std_logic_vector(6 downto 0);
sel:out
std_logic_vector(2 downto 0));
end;
architecture one of bjq7 is
begin
sel<='001';
process(input)
variable cnt:integer range 0 to 7;
begin
cnt:=0;
for i in 6 downto 0 loop
if input(i)='1'then
cnt1:=cnt1+1;
end if;
end loop;
if cnt>3 then y<='1';
else y<='0';
end if;
case cnt is
when
0=>led<='1111110';
when
1=>led<='0110000';
when
2=>led<='1101101';
when
3=>led<='1111001';
when 4
=>led<='0110011';
when
5=>led<='1011011';
when
6=>led<='1011111';
when
7=>led<='1110000';
when
others=>led<='0000000';
end case;
end process;
end;
程序3，，，，，，，，，，，，，，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bjq7 is
port (input:in std_logic_vector(6 downto 0);
cnt:out std_logic_vector(2
downto 0);
led:out
std_logic_vector(6 downto 0);
sel:out
std_logic_vector(2 downto 0));
end;
architecture one of bjq7 is
begin
sel<='001';
process(input)
variable cnt:integer range 0 to 7;
begin
cnt:=0;
for i in 6 downto 0 loop
if input(i)='1'then
cnt1:=cnt1+1;
elsif
input(i)='0'then
cnt2:cnt2+1;
else
cnt3:=cnt3+1;
end if;
end loop;
if cnt>3 then y<='1';
else y<='0';
end if;
case cnt is
when
0=>led<='1111110';
when
1=>led<='0110000';
when
2=>led<='1101101';
when
3=>led<='1111001';
when
4=>led<='0110011';
when
5=>led<='1011011';
when
6=>led<='1011111';
when
7=>led<='1110000';
when
others=>led<='0000000';
end case;
end process;
end;
