SystemC实例一:七段显示译码器
2010-04-28 16:39阅读：
SystemC实例一: 七段显示译码器
内容摘要：本文给出了SystemC的RTL级的描述例子，实现了七段显示译码器。并给出有关仿真结果及用Celoxica Agility
Compiler编译产生的Verilog输出。
目录：
1、七段显示码原理
2、解码模块seg7
3、测试模块（test_seg7)
4、主程序(sc_main)
5、仿真测试结果
6、模块seg7用Agility
Compiler编译产生的Verilog代码
一、七段显示码原理 七段显示管（共阴极）及编码如下图所示
（共阴极编码）
HGFE,DCBA
0 0x3F;
1 0x06;
2 0x5B;
3 0x4F;
4 0x66;
5 0x6D;
6 0x7D;
7 0x07;
8 0x7F;
9 0x6F;
a 0x77
b 0x7c
c 0x39
d 0x4e
e 0x79
f 0x71
二、解码模块seg7
SC_MODULE(seg7)
{
sc_in<sc_uint<4> > hex;
sc_out<sc_uint<7> > seg;
void run()
{
sc_uint<7> code[16] =
{0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x77,0x7c,0x39,0x4e,0x79,0x71};
seg.write(code[(int)hex.read()]);
}
SC_CTOR(seg7)
{
SC_METHOD(run);
sensitive << hex;
}
};
三、测试模块（test_seg7)
测试模块产生16个数，激励seg7，并打印出seg7模块解码输出
SC_MODULE(test_seg7)
{
sc_in<bool> clk;
sc_in<sc_uint<7> > seg;
sc_out<sc_uint<4> > data;
void run()
{
data.write((sc_uint<4>)0);
wait();
for(int i = 1;i< 16;i++)
{
data.write((sc_uint<4>)i);
cout << hex << i-1 << ' ' <<
hex
<< (int)seg.read() << endl;
wait();
}
cout << hex << 15 << ' ' <<
hex
<< (int)seg.read() << endl;
wait();
}
SC_CTOR(test_seg7)
{
SC_THREAD(run);
sensitive << clk.pos();
}
};
四、主程序(sc_main)
int sc_main(int argc,char *argv[])
{
sc_signal <sc_uint<7> > seg;
sc_signal <sc_uint<4> > hex;
sc_clock clk('clock',10,SC_NS);
seg7 s1('seg7');
test_seg7 t1('test');
s1.seg(seg);
s1.hex(hex);
t1.clk(clk);
t1.data(hex);
t1.seg(seg);
sc_start(200,SC_NS);
return 0;
}
五、仿真测试结果
六、模块seg7用Agility Compiler编译产生的Verilog代码
下面是用
Celoxica公司的Agility Compiler
1.3输出的Verilog（Celoxica已经把Handelc及Systemc的编译器卖给
AgilityDS，后者又被
Mentor
graphics收购了，而Mentor的收购只是为了消灭一个竞争对手，为Mentor自己的编译器让路）。
// SystemC module: 'seg7'
module seg7 ( hex, seg );
// interface
description
input [3:0] hex;
output [6:0] seg;
// Power cable
wire VCC;
// Ground cable
wire GND;
// One-Hot
Multiplexer
reg [6:0] seg_1;
// Constant value
wire [6:0]
ConstOut;
// Constant value
wire [6:0]
ConstOut_1;
// Constant value
wire [6:0]
ConstOut_2;
// Constant value
wire [6:0]
ConstOut_3;
// Constant value
wire [6:0]
ConstOut_4;
// Constant value
wire [6:0]
ConstOut_5;
// Constant value
wire [6:0]
ConstOut_6;
// Constant value
wire [6:0]
ConstOut_7;
// Constant value
wire [6:0]
ConstOut_8;
// Constant value
wire [6:0]
ConstOut_9;
// Constant value
wire [6:0]
ConstOut_10;
// Constant value
wire [6:0]
ConstOut_11;
// Constant value
wire [6:0]
ConstOut_12;
// Constant value
wire [6:0]
ConstOut_13;
// Constant value
wire [6:0]
ConstOut_14;
// Constant value
wire [6:0]
ConstOut_15;
// Constant value
wire [0:0]
ConstOut_16;
// Concatenation
wire [4:0]
DataWireId_7551;
// Decoder output
reg [15:0] R_0;
// Concatenation
wire [15:0]
MuxEnables;
always @ ( ConstOut or
ConstOut_1 or ConstOut_2 or ConstOut_3 or ConstOut_4 or ConstOut_5
or ConstOut_6 or ConstOut_7 or ConstOut_8 or ConstOut_9 or
ConstOut_10 or ConstOut_11 or ConstOut_12 or ConstOut_13 or
ConstOut_14 or ConstOut_15 or MuxEnables )
begin
// One-Hot
Multiplexer
case (
MuxEnables )
16'h8000: seg_1 <= ConstOut;
16'h4000: seg_1 <= ConstOut_1;
16'h2000: seg_1 <= ConstOut_2;
16'h1000: seg_1 <= ConstOut_3;
16'h800: seg_1 <= ConstOut_4;
16'h400: seg_1 <= ConstOut_5;
16'h200: seg_1 <= ConstOut_6;
16'h100: seg_1 <= ConstOut_7;
16'h80: seg_1 <= ConstOut_8;
16'h40: seg_1 <= ConstOut_9;
16'h20: seg_1 <= ConstOut_10;
16'h10: seg_1 <= ConstOut_11;
16'h8:
seg_1 <= ConstOut_12;
16'h4:
seg_1 <= ConstOut_13;
16'h2:
seg_1 <= ConstOut_14;
16'h1:
seg_1 <= ConstOut_15;
default: seg_1 <= 'bx;
endcase
end
assign MuxEnables = {
(R_0[0]), (R_0[1]), (R_0[2]), (R_0[3]), (R_0[4]), (R_0[5]),
(R_0[6]), (R_0[7]),
(R_0[8]), (R_0[9]),
(R_0[10]), (R_0[11]), (R_0[12]), (R_0[13]), (R_0[14]), (R_0[15])
};
assign VCC =
1'b1;
assign GND =
1'b0;
always @ (
DataWireId_7551 )
begin
//
Address decoder
case (
DataWireId_7551 )
5'b0: R_0 <= 16'h1;
5'b1: R_0 <= 16'h2;
5'b10: R_0 <= 16'h4;
