关于DC中的target_library和link_library的区别
2014-08-03 22:13阅读:
首先说的是,Synopsys规定,logic library
必须是db格式。包含target_library和link_library
关于target_library,DC规范中明确定义:
Design Compiler selects functionally correct gates from the target libraries to build a circuit during mapping. It also calculates the timing of the circuit by using the vendor-supplied timing data for these gates.
To specify the target libraries, use the target_library variable. Your should specify only the standard cell libraries that you want Design Compiler to use for mapping the standard cells in your design, such as combinational logic and registers. You should not specify any DesignWare libraries or macro libraries, such as pads or memories.
意思也就是说,target_library是DC在综合做mapping的时候,到这个目录下寻找使用到的标准单元库
关于link_library,一个完整的design的所有单元的的实例化,都必须要能够与相关library和引用的其他design连接起来。这个过程叫做linking the design or resolving references. To resolve references, Design Compiler uses the link libraries set by the foll
关于target_library,DC规范中明确定义:
Design Compiler selects functionally correct gates from the target libraries to build a circuit during mapping. It also calculates the timing of the circuit by using the vendor-supplied timing data for these gates.
To specify the target libraries, use the target_library variable. Your should specify only the standard cell libraries that you want Design Compiler to use for mapping the standard cells in your design, such as combinational logic and registers. You should not specify any DesignWare libraries or macro libraries, such as pads or memories.
意思也就是说,target_library是DC在综合做mapping的时候,到这个目录下寻找使用到的标准单元库
关于link_library,一个完整的design的所有单元的的实例化,都必须要能够与相关library和引用的其他design连接起来。这个过程叫做linking the design or resolving references. To resolve references, Design Compiler uses the link libraries set by the foll
