192.GCK得FPGA行为模型

wire clk_temp;
wire clk_in_inv;
assign clk_in_inv = !clk_in;
assign clk_temp = clk_in_inv ? (E | TE）: clk_temp;
assign Q = clk_in & clk_temp;
综合成latch + and结构
FPGA DFF命名FDxx， LATCH 命名LDxx